FPGA Mining

Introduction

The Proof-of-Work algorithm used by VeriBlock (vBlake) was designed to facilitate decentralization at every stage of the natural progression of mining hardware (CPU->GPU->FPGA->ASIC). The simplicity of the vBlake algorithm ensures that single developers or small development teams can produce near-optimal miners for any given hardware class, rather than allowing a single team or company make a massive breakthrough in the implementation and be the sole supplier of competitive miners.

Additionally, the algorithm is small enough to fit onto low-cost consumer grade FPGAs, rather than requiring expensive high-end chips. This allows hobbyist miners to mine VeriBlock in a cost-competitive way with large-scale mining operations. There are also plans to open-source an RTL implementation of vBlake in the near future to allow FPGA developers to easily add vBlake support to more FPGAs.

Pool Software

The built-in pool software included in VeriBlock's NodeCore software has a higher-difficulty setting to accomodate FPGA mining, see: HowTo_run_and_connect_to_PoW_Miner_pool#FPGA_Pools

Available FPGA Miners and Bitstreams

Bitstreams for BCU/VCU1525 cards are available from whitefire as well as from Allmine.

Additionally, the Blackminer F1 and F1-single (and likely F1+) support vBlake, as well as their upcoming entry-level F1 Mini.

FAQ

Is there source code

An FPGA mining core for vBlake (the PoW algorithm for the VeriBlock blockchain):

https://github.com/VeriBlock/vBlake-RTL

Is VeriBlock FPGA resistant?

No.

VeriBlock welcomes the most hashing power to secure the blockchain, and FPGAs are inevitable. Much like we are not "GPU resistant", we are also not "FPGA" resistant.

Appendix

vBlake-RTL release message

Initial vBlake-RTL repo shipped on 5/9/2019, with message on Discord:

**Open-source FPGA mining core for vBlake**

The VeriBlock team is excited to release a free and open-source FPGA mining core for vBlake (the PoW algorithm for the VeriBlock blockchain)!

Github repo: https://github.com/VeriBlock/vBlake-RTL

We designed vBlake to democratize mining at every stage of the mining hardware evolution by being small, straight-forward, and benefitting from existing optimization work already done with BLAKE2b. This approach allows an engineer at any hardware level (CPU, GPU, FPGA, ASIC) to create optimized miners easily, rather than centralizing miner production into the hands of a select few elite engineers/groups who crack the case on significant optimizations.

Most FPGA-mineable blockchain projects only have closed-source FPGA software available, centralizing mining to a small number of FPGA models and subjecting their users to high dev-fees. Rather than following that pattern, we are releasing open-source RTL code for vBlake, helping to fulfill the decentralization goals of the project. This RTL implementation of vBlake makes implementing VeriBlock mining far easier on a wide variety of FPGAs for which public bitstreams don't exist, or have dev fees attached. Because of its small footprint, vBlake fits onto affordable FPGA chips which are accessible to miners of any budget.

We look forward to ongoing collaboration with the open-source community to improve the design and make public bitstreams for a variety of boards available.

Much thanks to Michael Sanders, a long-time community developer for the VeriBlock Blockchain Project, for his hard work optimizing the FPGA core.

About Michael Sanders: Michael is a Google® (Alphabet Inc. (Nasdaq: 
GOOG)) senior software engineer motivated by a passion for technology. 
He unravels complexity and strives for elegant solutions to large scale problems. His extensive experience spans areas including developer tools, distributed systems, embedded systems, operations, and programmable logic.

To learn more about FPGA Mining for VeriBlock, see: https://wiki.veriblock.org/index.php?title=FPGA_Mining